Embodiments of the present invention relate to a non-volatile memory device and a sensing method thereof, and more specifically, to a non-volatile memory device configured to sense multi-level data using resistance variation.
Memory devices may be classified into volatile memory devices and non-volatile memory devices. Non-volatile memory devices include a non-volatile memory cell capable of preserving stored data even when not powered. For example, a non-volatile memory device may be implemented as a flash random access memory (flash RAM), a phase change random access memory (PCRAM), or the like.
A PCRAM includes a memory cell that is implemented using a phase change material such as germanium antimony tellurium (GST), wherein the GST changes to a crystalline phase or an amorphous phase if heat is applied to the GST, thereby storing data in the memory cell.
A non-volatile memory device (e.g., a magnetic memory, a phase change memory (PCM), or the like) has a data processing speed similar to that of a volatile RAM device. The non-volatile memory device also preserves data even when power is turned off.
FIGS. 1A and 1B illustrate a conventional phase change resistor (PCR) element 4.
Referring to FIGS. 1A and 1B, the PCR element 4 includes a top electrode 1, a bottom electrode 3, and a phase change material (PCM) layer 2 located between the top electrode 1 and the bottom electrode 3. If a voltage and a current are applied to the top electrode 1 and the bottom electrode 3, a current signal is provided to the PCM layer 2, and a high temperature is induced in the PCM layer 2, such that the electrical conductive state of the PCM layer 2 changes depending on resistance variation.
FIGS. 2A and 2B illustrate a phase change principle of the conventional PCR element 4.
Referring to FIG. 2A, if a low current, smaller than a threshold value, flows in the PCR element 4, the PCM layer 2 has a temperature suitable for a crystalline phase. Therefore, the PCM layer 2 changes to the crystalline phase, such that it becomes a low-resistance phase material. As a result, a current may flow between the top electrode 1 and the bottom electrode 3.
On the other hand, as shown in FIG. 2B, if a high current, greater than the threshold value, flows in the PCR element 4, the PCM layer 2 has a higher temperature than a melting point. Therefore, the PCM layer 2 changes to an amorphous phase, such that it becomes a high-resistance phase material. As a result, it is difficult for the current to flow between the top electrode 1 and the bottom electrode 3.
As described above, the PCR element 4 can store data corresponding to two resistance phases as non-volatile data. For example, assuming that in one case the PCR element 4 has a low-resistance phase that corresponds to data ‘1’ and in the other case the PCR element 4 has a high-resistance phase that corresponds to data ‘0’, the PCR element 4 may store two logic states of data.
In addition, a phase of the PCM layer (i.e., a phase change resistive material) 2 is not changed although the phase change memory device is powered off, such that the aforementioned data can be stored as non-volatile data.
FIG. 3 illustrates a write operation of a conventional PCR cell.
Referring to FIG. 3, when a current flows between the top electrode 1 and the bottom electrode 3 of the PCR element 4 for a predetermined time, heat is generated.
When a low current, smaller than a threshold value, flows in the PCR element 4 during the predetermined time, the PCM layer 2 has a crystalline phase formed by a low-temperature heating state, such that the PCR element 4 becomes a low-resistance element having a set state.
On the other hand, when a high current, greater than the threshold value, flows in the PCR element 4 during the predetermined time, the PCM layer 2 has the amorphous phase formed by a high-temperature heating state, such that the PCR element 4 becomes a high-resistance element having a reset state.
Accordingly, in order to write data of the set state during the write operation, a low voltage is applied to the PCR element 4 for a long period of time. On the other hand, in order to write data of the reset state during the write operation, a high voltage is applied to the PCR element 4 for a short period of time.
The PCR memory device applies a sensing current to the PCR element 4 during a sensing operation, such that it can sense data stored in the PCR element 4.
FIG. 4 is a circuit diagram illustrating a sensing unit 10 of a conventional phase change memory device.
Referring to FIG. 4, the sensing unit 10 includes a read drive unit 11, a precharge unit 12, a clamping unit 13, a reference voltage selection unit 14, and a sense amplifier (sense-amp) (SA).
A unit cell UC includes a phase change resistor (PCR) element and a diode D.
The read drive unit 11 drives a high voltage VPPSA in response to a current driving signal so that it outputs a sensing voltage SAI.
The precharge unit 12 precharges the sensing voltage SAI with a high voltage VPPSA level in response to a precharge signal.
The clamping unit 13 clamps a voltage level of the sensing voltage SAI in response to a clamping control signal CLM during a sensing operation.
The reference voltage selection unit 14 selects one of a plurality of reference voltages REF0 to REF2 and outputs the selected reference voltage REF to the sense amplifier SA.
The sense amplifier SA compares the selected reference voltage REF with the sensing voltage SAI in response to a sense-amp enable signal SEN, and amplifies the compared result to output an amplified signal. The sense amplifier SA receives the sensing voltage SAI through a positive (+) input terminal, and receives one of the reference voltages REF0 to REF2 through a negative (−) input terminal.
If a resistance state of a cell is determined by a write operation, the precharge unit 12 precharges a read path with the high voltage (VPPSA) level, and is then deactivated. In addition, the read drive unit 11 provides the read path with a current to be used for the sensing operation.
A level of the sensing voltage SAI may be determined, as shown in FIG. 5, according to the relationship between a threshold voltage Vt of an NMOS transistor contained in the clamping unit 13 and a gate source voltage Vgs formed in a bit line BL in response to cell resistance.
FIG. 5 shows the distribution of cell resistance and a sensing output level in the phase change memory device shown in FIG. 4.
At least two read operations are required to sense data having 2 bits from one cell. Specifically, when sensing the 2-bit data in one cell, the read operation is performed by distinguishing four states from one another.
That is, when sensing the 2-bit data in one cell, one of four states “00”, “01”, “10” and “11” is identified according to a resistance value of data stored in the cell. In order to identify such four-state data, three reference voltages REF0 to REF2 are required.
If a value of the cell data is less than the reference voltage REF0, data “00” is identified. If the cell data value is higher than the reference voltage REF0, data “01” is identified. If the cell data value is higher than the reference voltage REF1, data “10” is identified. If the cell data value is less than the reference voltage REF2, data “10” is identified. If the cell data value is higher than the reference voltage REF2, data “11” is identified.
In this way, if four resistance states are distinguished from one another, the read operation needs to be performed three times. In order to perform the read operation three times, the reference voltage selection unit 14 selects one of the reference voltages REF0 to REF2, and outputs the selected voltage to the sense amplifier SA. Then the sense amplifier SA senses the voltage level of the sensing voltage SAI, which is determined by a resistance value of data stored in the cell.
However, if the number of bits of read data increases, the number of times the read operation is performed for one cell should be increased, or several reference voltage levels should be applied according to a sensing scheme, resulting in difficulty in application or implementation.
That is, when using several reference voltage levels, the reference voltage selection unit 14 take longer to change a reference voltage. Furthermore, when changing the reference voltage, the occurrence of noise may increase. In addition, if the number of reference voltage levels increases, an area for setting reference lines increases.
FIG. 6 is a conceptual diagram illustrating a verification operation performed to improve the distribution of cell resistance in the phase change memory device shown in FIG. 4.
When sensing multi-level data, the verification operation is performed by reading the position of a cell where a write operation is completed, thereby determining whether to perform an additional write operation.
In order to improve the distribution of cell resistance, it is necessary to perform a read operation after changing the reference levels REF0 to REF2 to verification levels, as shown in FIG. 6.
In this case, the reference voltage REF0 is changed to verification levels Verify01 and Verify0R, the reference voltage REF1 is changed to verification levels Verify1L and Verify1R, and the reference voltage REF2 is changed to verification levels Verify2L and Verify2R.
However, in order to perform the verification operation, the read operation must be performed at least six times. In addition, in order to change three reference voltage levels REF0 to REF2 to the verification levels, additional control is required.
Therefore, in order to perform such a verification operation, the number of read operations increases. If the reference voltage level is changed, an increase in noise occurs. In addition, it takes a long time to change the reference voltage level, and an area of a driver for controlling verification levels increases.